1. Technical Field
The present invention relates to a device for protecting electric circuits against faults, specifically for switching power electronic circuits.
2. Description of the Related Art
Devices for protecting various types of integrated electronic circuits, specifically for integrated power circuits of the switching type, are known in the state of the art. Said devices control the turning off of the transistors of the integrated power circuits in response to a fault of the power circuit itself. For example, as shown in FIG. 1, the power stage of an integrated circuit may include a half-bridge with two power transistors, one high side HS and one low side LS, arranged between a power voltage Vdd and ground GND and appropriately driven by a driving circuit 1. In turn, the two transistors drive a load 2 consisting, for example, of a motor. The driving circuit 1 normally supplies the signals to the transistors LS and HS to switch them on or off.
The power stage may suffer faults during its use, e.g., overcurrent, overvoltage, or excessive temperature. For such a reason, a protection circuit is normally inserted. Said protection circuit includes a fault detector 4 and a circuit which operates on the driving circuit of the power stage in response to the detection of the fault. The action operated by the protection circuit is normally that of causing the shutdown of the power stage by means of an input signal SD into the circuit 1.
The protection circuit in FIG. 1 normally includes a comparator 3 which is adapted to compare the signal CIN detected by the fault detector with a reference signal REF, and is adapted to drive a MOS transistor M arranged between the input terminal of the circuit 1, at which the shutdown signal SD is present, and the ground GND. When the signal CIN is higher than the signal REF, the transistor M is switched on and the signal SD, i.e., the signal for turning off the transistors of the power stage, is taken to a low level, i.e., to ground GND.
A problem of such a protection circuit is due to the delay to take the SD signal to a low level. Indeed, an external network, including a resistor R connected to the power voltage Vdd and a capacitor C connected to ground GND, is connected to the drain terminal of the transistor M and thus the signal SD is switched to a low level according to the time constant Ron_M*C, wherein Ron_M is the switch-on resistance of the transistor M. In such a manner, the shutdown signal SD will be sent to the control circuit of the power stage with a certain delay from said time constant which depends on the external network. As a result, the selection of a high-value external capacitive component C is used but, on the other hand, the capacity of taking current of the transistor M limits the maximum obtainable value of the external capacitive component. Therefore, the protection circuit intervention always occurs with a certain delay after detecting the fault, and said delay may cause faults to the power stage.